This paper describes a hardware implementation of the modular multiplication using the Adapted Modular Number System (AMNS) representation of large integers. We propose a novel adaptation of the FIOS block Montgomery multiplication fitted to the AMNS representation. We explore multiple operations schedulings for the design of systolic architectures well suited to this FIOS algorithm. Our scalable implementation targets Ultrascale FPGA devices and takes full advantage of modern DSP48E2 Slices. We provide open-source, ready to use designs which are scalable to any width of the operands and a large range of AMNS parameters. Our designs can perform 256, 512, 1024, 2048 and 4096 bits modular multiplications in 0.178, 0.362, 0.764, 1.57 and 2.96 µs using 18, 35, 65, 125 and 245 DSP block respectively. They can allow for an improvement in computing speed and DSP AT (Digital Signal Processing block Area-Time product) of up to 17% and 13% respectively compared to state of the art implementations.